Conventionally, solid-state image sensors have been frequently used in various solid-state image pickup apparatuses for capturing exterior image information and converting it to electric signals, such as digital cameras and facsimiles. Solid-state image sensors of this type are roughly divided into the so-called “line sensor” having pixel regions aligned in one direction (i.e., one-dimensionally) and the so-called “area sensors” having pixel regions arranged in an area (i.e., two-dimensionally). Conventional solid-state image sensors of this type generally have the following configuration.
Specifically, semiconductor light-receiving elements are regularly arranged corresponding to pixel regions. Light from an exterior image is separately received by the respective elements in the pixel regions and is converted to electric signals according to the intensity of the light. In other words, image information is photoelectrically converted by the elements in the respective pixels. Thereafter, the electric signals thus obtained are transferred to a predetermined signal processing circuit by a signal transfer circuit using Charge-Coupled Devices (CCDs) or shift registers, and is subjected to a predetermined signal processing in the signal-processing circuit, thereby reproducing the image. Additionally, as the semiconductor light-receiving elements, for example, photodiodes (PDs), phototransistors, or Metal-Oxide Semiconductor (MOS) capacitors are used.
Moreover, examining the packaging style of the conventional solid-state imaging sensors of this type, the semiconductor light-receiving elements, the signal transfer circuit and the signal processing circuit are formed in a semiconductor chip. The chip is mounted in a package having a window for introducing light. Light from an exterior image is temporarily taken in the package by way of the window and thereafter, is irradiated to the individual light-receiving elements in the chip by way of a light-introducing path or paths formed in the package. To shorten the light-introducing path(s) as much as possible, the elements in the chip are located near the window of the package.
On the other hand, in recent years, solid-state image sensors with a three-dimensional structure formed by stacking semiconductor chips were announced. For example, Kurino et al. announced “Intelligent Image Sensor Chip with Three-Dimensional Structure” in 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4 published in 1999.
This image sensor chip has a four-layer structure, where a processor array and an output circuit are located in the first layer, data latches and masking circuits are located in the second layer, amplifiers and analog-to-digital converters are located in the third layer, and an image sensor array is located in the fourth layer. The uppermost surface of the image sensor array is covered with a quartz glass layer containing a microlens array. The microlens array is formed on the surface of the quartz glass layer. A photodiode is formed as the semiconductor light-receiving element in each image sensor of the image sensor array.
In addition, the respective layers constituting the four-layer structure are mechanically connected to each other with an adhesive, and are electrically connected to each other with buried interconnections using conductor plugs and microbump electrodes contacted with the interconnections.
Lee et al. announced “Development of Three-Dimensional Integration Technology for Highly Parallel Image-processing Chip” in Japan Journal of Applied Physics, Vol. 39, pp. 2474-2477, published in April 2000.
The image sensor chip of Lee et al. has approximately the same configuration as the solid-stage imaging sensor announced by Kurino et al. in the above-described treatise.
With the above-described conventional solid-state image sensors having a popular configuration, viewing from an aspect of configuration, exterior optical information is sensed by the light-receiving elements in the semiconductor chip by way of the window of the package, thereby obtaining the electric signals corresponding to the optical information. Thereafter, the electric signals are successively transferred to the signal processing circuit with the signal transfer circuit using CCDs or shift-registers. Therefore, time delay occurs from the reception of light by the light-receiving elements to the start of signal processing by the signal processing circuit and as a result, there is a problem that a sufficiently high operation speed (e.g., an operating frequency in the order of GHz) satisfying the recent demand of raising the signal processing rate is not obtainable. Moreover, there is another problem that the size of the solid-state image sensor is large because the package and the semiconductor chip are separately formed.
Viewing from an aspect of the fabrication process sequence, it is required that the package is formed separately from the semiconductor chip and then, the chip is mounted in the package. Thus, there is a problem that the fabrication process sequence is complicated.
Unlike this, with the solid-state image sensors disclosed in the above-described two treatises, the uppermost surface of the image sensor array is covered with the quartz glass layer, and the microlens array is formed on the said surface of the quartz glass layer. The necessary signal processing circuits (e.g., processors and amplifiers) are built in. Therefore, the problem about the operation speed in the above-described conventional image sensors is solvable.
However, there is a problem that formation of the microlens array on the surface of the quartz glass layer is not easy and that sophisticated technologies are required for realizing it. Furthermore, since a plurality of semiconductor chips are stacked to form the three-dimensional structure, simplification of the fabrication process sequence is required as well.